A Parallel ATPG Algorithm Based on Big Function Block

查看全文 作　　者：Zhide [1]Zeng;Pengxia [1]Liu 机构地区：[1]School of Computer,National University of Defense Technology ChangSha,Hunan,China,410073 出　　处：《湖南大学学报(自然科学版)》索引2000年第27卷第S2期,共6页 基　　金：Supported by National Natural Science Founding of China. 摘　　要：The paper presents a parallel ATPG algorithm - PTGBP, which aims at decreasing the complexity of the ATPG by partitioning circuit under test (CUT) to big function blocks (BFB) and processing them parallelly. PTGBP adopts hybrid circuit mode and hybrid fault model, and organizes the parallel course in term of master/slave mode. Master processor loads the whole netlist of CUT based on BFB, every slave processor loads logic level (gate/function block/basic logic units) netlist of a BFB. Test generation (TG) uses BFB input/output s-a-0/s-a-1 fault model; fault simulation uses logic level single stuck fault model. Master controls the PTGBP’s running course and ensures the correctness of its running result; slaves provide the results of fault sensitization compatible computation and fault simulation to master parallelly. PTGBP algorithm is under implementation. 关 键 词：parallel ATPG big function block register-transfer level