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| 1 | System-level buffer allocation for application specific networks on chip router design显示文摘 | Hu Jingcao Ogras U Y Marculescu R | 2006 | IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems2006，25，3： | 1 |
| 2 | System-level buffer allocation for application-specific networks-on-chip routerdesign 显示文摘 | Hu J Ogras U Y Marculeseu R | 2006 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2006，25，12： | 1 |
| 3 | System-levelbuffer allocation for application specific networks onchip router design 显示文摘 | Hu J ingcao Ogras U Y Marculescu R | 2006 | IEEE Transactions on Computer Aided Design of Integrated Circuit s and Systems2006，25，3： | 1 |
| 4 | Computation and communication refinement for multiprocessor SoC design:a systemlevel perspective显示文摘 | MARCULESCU R OGRAS U Y ZAMORA N H | 2006 | ACM Trans on Design Automation of Electronic Systems2006，11，3： | 1 |
| 5 | System-level buffer allocation for application-specific networks-on-chip router design显示文摘 | Hu J Ogras U Y Marculescu R | 2006 | IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems2006，25，3： | 1 |
| 6 | On-chip communication architecture exploration: a quantitative evaluation of point-to-point, bus and network-on-chip approaches显示文摘 | LEE H G CHANG N OGRAS U Y | 2007 | ACM Transactions on Design Automation of Electronic Systems2007，12，3： | 1 |
| 7 | Energy-and performance-aware incremental mapping for networks on chip with multiple voltage levels显示文摘 | Chou C L Ogras U Y Mareulescu R | 2008 | IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems2008，27，10： | 1 |
| 8 | Energy- and Performance-Aware Incremental Mapping for Networks on Chip with Mlutiple Voltage Levels显示文摘 | Chou C L Ogras U Y Marculescu R | 2008 | IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems2008，27，10： | 1 |
| 9 | De- sign and management of voltage-frequency island parti- tioned networks-on-chip 显示文摘 | Ogras U Y Marculescu R Marculescu D | 2009 | IEEE Transactions on Very Large Scale Integration Systems2009，17，3： | 1 |
| 10 | Outstanding research problems in No C design:system,micro-architecture,and circuit perspectives显示文摘 | MARCULESCU R OGRAS U Y PEH L S | 2009 | IEEE Transactions on Computeraided Design of Integrated and Systems2009，28，1： | 1 |
| 11 | On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches显示文摘 | LFF H G CHANG H OGRAS U Y | 2007 | ACM Transactions on Design Automation of Electronic Systems2007，12，3： | 1 |
| 12 | On-Chip communication architecture exploration:A quantitative evaluation of point- to-polnt,bus,and network-on-chlp approaches显示文摘 | Lee Hyung Gyu Chang Naehyuck Ogras U Y | 2007 | ACM Transactions on Design Automation of Electronic Systems2007，12，3： | 1 |
| 13 | On-chipcommunication architecture exploration:Aquantitative evaluation of point-to-point,bus,andnetwork-on-chip approaches显示文摘 | LEE H G CHANG N OGRAS U Y | 2007 | ACM Transactionson Design Automation of Electronic Systems2007，12，3： | 1 |
| 14 | Design and management of voltage-frequency island partitioned networks -on-chip显示文摘 | Ogras U Y Marculescu R Marculescu D | 2009 | IEEE Transactions on Very Large Scale Integration ( VLSI) Systems2009，17，3： | 1 |
| 15 | Outstanding research problems in NoC design: System, microarchitecture, and circuit perspectives 显示文摘 | Marculescu R Ogras U Y Peh L-S | 2009 | IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems2009，28，1： | 1 |
| 16 | Energy-and performance-aware incremental mapping for networks on chip with multiple voltage levels显示文摘 | Chou C L Ogras U Y and Marculescu R | 2008 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2008，27，10： | 1 |
| 17 | System level buffer allocation for application specific networks-on-chip router design 显示文摘 | Hu J Ogras U Y Marculescu R | 2006 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2006，25，12： | 1 |
| 18 | On-chip communication architecture exploration:A quantitative evaluation of point-to-point,bus,and network-on-chip approaches显示文摘 | LEE H G CHANG N OGRAS U Y | 2007 | ACM Transactions on Design Automation of Electronic Systems2007，12，3： | 1 |
| 19 | Design and management of voltage-frequency island partitioned networks on chip显示文摘 | Ogras U Y Marculescu R Marculescu D | 2009 | IEEE Trans on VLSI Systems2009，17，3： | 1 |
| 20 | Outstanding re- search problems in NoC design: System, microarchitecture, and cir- cuit perspectives 显示文摘 | MARCULESCU R OGRAS U Y PEH L-S | 2009 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2009，28，1： | 1 |
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